United States

High-brightness photoemitters can be employed as electron sources in ultrafast electron diffraction and X-ray free-electron lasers, energy recovery linacs, electron microscopes, electron beam lithography, space propulsion and high-power microwave devices. To yield high quantum efficiencies, high brightness beams require rapid response times and low mean transverse energies (MTE). Recently, negative electron affinity (NEA) photocathodes, consisting of a GaAs wafer and a Cs/O surface layer, have been reported to exhibit both reasonably low MTE and good external quantum efficiencies (EQE) of ~10 ~-10 “. However, NEA cathodes are rarely used due to their significantly complex fabrication process which includes high temperature processing steps, entirely in-situ activation as well as ultra-high vacuum storage and operating pressures. Their stability is not also up to the mark. In this investigation, we have fabricated a Hot Electron Laser Assisted Cathode (HELAC) using electronically tunable negative electron affinity silicon surface. Briefly, the device consists of a three-layer stack of (i) a semiconductor, which absorbs incident photons, (ii) a monolayer of graphene, which acts as the gate, and (iii) an insulator, which allows a voltage drop between the semiconductor and graphene. In this device, an electric field is generated by applying a bias voltage between the semiconductor and graphene which mimics the surface dipole field in an NEA photocathode. Electrons injected into the graphene do not require transport to the emitting surface due to the monolayer thickness of the graphene. This device is air stable with a simple ex-situ fabrication flow while preserving the advantages of NEA photocathodes. We have demonstrated an initial proof-of-concept HELAC device with a psilicon substrate, silicon oxide insulator and monolayer graphene stack and evaluated its performance using a 405 nm CW laser at ~40 mW of incident power. Despite having a non-optimized structure, this device has exhibited a current of ~70 yA (~1.1 mA/cm?), resulting in an EQE of ~0.5%. Semiconductor modeling indicated that EQEs of ~10% and response times in the 1-10 ps range are plausible for this device. Additionally, it is expected that low-MTE is achievable by optimizing the quality of the insulator, the barrier height, and the tunneling mechanism. This is analogous to Cs-based NEA devices, where low MTEs are attainable despite a large electric field which is developed due to the surface dipole.

EMC 2022

Hot Electron Laser Assisted Cathode using Electronically Tunable Negative Electron Affinity Silicon Surface

negative electron affinity

photoemitter

graphene

After two years of virtual conferences, we're excited to host EMC 2022 in person at The Ohio State University in Columbus, Ohio. In addition to cutting-edge technical presentations given in multiple parallel sessions, opportunities to network with colleagues will be present throughout the conference. The size and format of the meeting makes networking easy, whether you have been coming to the conference for many years or are a first-time attendee.

EMC is coordinated with the Device Research Conference (DRC), which will be held the same week, from June 26-29. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

For information on the 80th Device Research Conference, please visit the DRC 2022 website.



The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

technical paper

Here, we demonstrate chemical potential control as an effective tool to suppress compensation in Mgdoped nitrogen-polar (N-polar) gallium nitride (GaN) films grown by metalorganic chemical vapor deposition (MOCVD). An increase in nitrogen chemical potential obtained by increasing the process supersaturation is shown to systematically reduce the incorporation of compensating oxygen and nitrogen-vacancy point defects. This is confirmed by photoluminescence and temperature-dependent Hall effect measurements. The suppressed compensation led to an order of magnitude improvement in p-type conductivity with the room-temperature hole concentration, mobility, and resistivity measuring 6x10" cm ™~, 9 cm*/Vs, and 1.1 ohm-cm, respectively. These results are paramount in the pathway towards N-polar GaN power and optoelectronic devices. GaN with N-polar orientation has attracted growing interest toward the development of high-performance electronic and optoelectronic devices such as high-frequency high electron mobility transistors (HEMTs), solar cells, longwavelength LEDs, and ultraviolet photocathodes. A reversal of polarization field direction in N-polar GaN from its metal-polar counterpart allows for device designs that lead to improved performance, for example, enhanced carrier extraction efficiency in InGaN solar cells, enhanced hole injection, suppressed electron overflow and decreased droop in LEDs, improved confinement in the two-dimensional electron gas channel in AlGaN/GaN HEMTs, and improved transistor performance in polarization-engineered tunnel field-effect transistors (T-FETs). These novel device applications based on N-polar GaN can be further improved and optimized with the realization of low-resistivity p-type material. For example, achieving a steep device turn-on in T-FETs necessitates low resistance p-GaN layers, whereas high hole and electron concentrations are required near the p-n junction for optimal band alignment in these devices. Achieving efficient p-type doping in GaN is understood to be challenging due to an interplay between large Mg acceptor ionization energy (150-220 meV), incorporation of compensating point defects and point defect complexes during epitaxial growth, and low mobility values of holes as compared to electrons. Moreover, N-polar GaN offers added material challenges that need to be addressed to achieve high p-type conductivity. For instance, if not controlled, N-polar GaN grows with a rough surface morphology characterized by hexagonal hillocks, and high unintentional defect incorporation, notably oxygen, which incorporates at concentrations >10 ~ cm™~. Oxygen on the nitrogen site (O7) acts as a shallow donor in N-polar GaN with an activation energy of ~29 meV which leads to significant difficulties in achieving p-type conductivity. In addition, the incorporation of nitrogen-vacancy (V)))-related compensating defects is favored in p-type GaN due to low formation energy. While much work has focused on pdoping of Ga-polar GaN, to date, comprehensive electrical characterization and compensation control in p-type Npolar GaN is lacking in the literature. The chemical potential control (CPC) is a predictive approach wherein the dependence of the defect formation energy is theoretically estimated as a function of MOCVD growth parameters. These growth parameters are, for example, the V/IIl ratio, diluent gas, temperature, pressure, and input partial pressures of gas species. Instead of these individual MOCVD “knobs”, supersaturation is employed as a representative thermodynamic parameter. Following the CPC framework, increasing the supersaturation can be shown to increase the formation energy of both compensating defects, On and Vn: In this work, we demonstrate the utility of the CPC scheme in reducing the compensation in ptype N-polar GaN to realize state-of-the-art hole concentration and resistivity.

Chemical Potential Control in p-Type N-Polar GaN

The heterogeneous integration of IIl-nitride materials with other semiconductor systems for electronic devices is attractive because it combines the excellent electrical properties of the Ill-nitrides with other device platforms. Pursuing integration through metalorganic chemical vapor deposition (MOCVD) is desirable because of the scalability of the technique, but the high temperatures required for the MOCVD growth of Ill-nitrides (>1000 °C) are incompatible with heteroepitaxy on some semiconductor systems and fabricated wafers. Thus it is critical to develop IIl-nitride films with good electrical properties at growth temperatures compatible with temperature sensitive substrates. High crystal quality GaN films with reduced impurity levels have been achieved at temperatures as low as 500 °C using pulsed growth methods such as atomic layer epitaxy and flow modulation epitaxy (FME). However, the electrical behavior of doped LT Ill-nitride films is relatively unexplored. In this work, thin Si-doped LT GaN films were grown at 550 °C by atmospheric pressure MOCVD using an FME scheme. Triethylgallium and ammonia were used as the GaN precursors and disilane as the Si dopant. Because of the very low growth rate (0.006 A/s), 1200 FME cycles resulted in approximately 16 nm-thick films. Two different FME Si-doping schemes were investigated. The first series varied the fraction of cycles in which disilane was injected into the growing film. Samples were grown with disilane injected every 20, 10, 5, 3, 2, and 1 cycle. The second series varied the disilane flow while using the standard frequency of disilane injection (1 in 5 cycles). Samples were characterized by Hall measurements and secondary ion mass spectrometry (SIMS). For the disilane injection series films, electron concentrations up to 6.97 x 4018 om”? were achieved, with electron mobilities from 34 to 119 cm vi sl The peak electron concentration was achieved for the sample with disilane injected in 1/3 of FME cycles during growth. The charge dropped off for samples with higher frequencies of disilane injection, likely because of degraded morphology. The Si concentrations measured by SIMS were somewhat higher than the electron concentrations measured by Hall. The background atmospheric impurity concentrations averaged 2.1 xX 1017 em’? for oxygen and 3.9 x 10 0 cm ~ for carbon, with no apparent dependence on Si concentration. The disilane flow series resulted in films with electron concentrations from 5.98 x 10 ~ cm ~ to 5.91 x 10'9 om”? and electron mobilities from 52 to 115 cm? vi s |, with the highest charge achieved with the highest disilane flow. The sheet resistance of this sample was 1068 Q/#, which is comparable to low resistance GaN films grown at high temperature, which range from 100-500 Q/#. These results demonstrate the potential for LT Ill-nitrides in electronics applications. This work supported in part by Intel Corporation and the Solid State Lighting and Energy Electronics Center.

High to Ultrahigh Si-Doped GaN Grown by Metalorganic Chemical Vapor Deposition at 550 °C for Heterogeneous Integration

III nitride semiconductors have recently disrupted several industries and have remarkable potential to address unmet needs in electronics and optoelectronics. While gallium nitride (GaN) is the champion nitride material in solid state lighting and high power and high frequency electronics, there is abundant untapped potential in other nitrides that are otherwise harder to grow and to gain control over their electronic properties. Among these, Indium nitride (InN) that promises the highest saturation velocity in the nitride group poses two difficult challenges to realize its potential: (1) The epitaxial growth of high-quality InN films or structures is very challenging due to the competitive decomposition of InN at the temperatures for which efficient cracking of nitrogen sources occur, and (2) the difficulty in growing a larger bandgap barrier layer at the surface which requires even higher temperatures than the InN decomposition temperature, and with the absence of such layer, surface Fermi energy pinning challenges the modulation of the electron charge density to make functional transistor devices from any grown InN layers. Yes, there has been outstanding progress in the growth of InN layers by molecular beam epitaxy or plasma assisted metalorganic chemical vapor deposition (MOCVD), but the growth of smooth InN surfaces and the growth of larger barrier layers on InN has not been accomplished before: This work demonstrates by standard pulsed MOCVD growth the ability to grow defect free InN structures with smooth surfaces and the ability to grow with control GaN barrier layers and to demonstrate excellent transport characteristics in these structures. We hypothesized that coalescence of InN islands in constrained geometries such as lateral Fins can accelerate the formation of void-free and defect free InN growth within the first few nanometers of grown InN. We further hypothesized that we can raise the effective V/III ratio by pulsing the tri-methyl-indium source to avoid droplet formation, ripening and segregation which otherwise leads to the growth of defective and porous InN layers. We validated these hypotheses by studying growth parameters and Fin widths in the range of 60 nm to 2000 nm (and control planar samples) and demonstrated InN Fins with defect-free surfaces and single crystal structures. Unannealed Ti/Au metal contacts on packed InN Fin arrays resulted in effective (un-corrected) specific contact resistance of approximately 6Q¢um, which is much smaller than that obtained for current GaN ohmic contacts, with an extracted contact transfer length less than 1pm. To leverage these structures for high electron mobility applications and un-pin their surface Fermi energy, we successfully grew in-situ GaN/InN heterostructure without compromising the smooth InN surface. Transmission electron Microscopy showed clear interface between GaN and InN and single crystal structure. We then demonstrated that GaN can be selectively etched in the source/drain regions of the heterostructure and that unannealed Ti/Au metal contacts retain their low specific contact resistance on these structures. We are now investigating the fabrication of GaN/InN and AIN/INN HEMTs and their DC/RF performance.

Demonstration of Single Crystal InN & GaN/InN Heterostructures by MOCVD

Nanoscale spintronics devices can revolutionize computer logic and memory units. Interestingly, paramagnetic nanostructures strongly exchange coupled with two ferromagnetic electrodes can yield novel forms of magnetic materials. However, there is a knowledge gap about the role of the number of paramagnetic nanostructures on the various properties of whole spintronics devices. To make this study relevant to the experimentally attainable device structure, we focus on the magnetic tunnel junction (MTJ) based spintronics device architecture. Under this approach, paramagnetic nanostructures are placed along the MTJ perimeter. We assume that the tunnel barrier of the MTJ does not allow any leakage current or exchange coupling, and paramagnetic nanostructures dictate the exchange coupling between the ferromagnetic electrodes. Also, the width of the ferromagnetic electrodes is governed by the number of paramagnetic nanostructures. This study systematically varied the number of nanostructures from 1 to 625 (25 x 25). The overall device was represented by a Heisenberg 3D model containing five atomic layer thick ferromagnetic electrodes. The number of paramagnetic nanostructures governed the width of the ferromagnetic electrodes. For instance, the device with a single nanostructure and 5 x 5 nanostructure possessed FM electrodes with one atom and five atom width, respectively. The paramagnetic nanostructures — sandwiched between the two FM electrodes — were placed on the perimeter of the 5 x 5 square with an empty space inside the square. The empty space shows the presence of an insulating spacer needed to provide the physical separation to enable paramagnetic nanostructures to control the spin dynamics of the device . The strength of exchange coupling between the paramagnetic nanostructure and ferromagnetic electrodes was fixed to be antiferromagnetic, consistent with experimental observations with analogous devices . We observed that thermal energy strongly influenced the temporal evolution of the equilibrium state of devices. The device with a single paramagnetic nanostructure struggled to align the left ferromagnet (Left-FM) and right ferromagnetic electrode (Right -FM) at low thermal energy of kT = 0.01. At higher thermal energy, devices with a single paramagnetic nanostructure underwent significant fluctuations. The device with a 5 x 5 paramagnetic structure also had difficulty attaining the fully antiparallel state at low thermal energy of kT = 0.01. However, at higher thermal energy of kT = 0.1, 5 x 5 paramagnetic nanostructure started producing conclusive antiparallel ferromagnetic electrodes. This paper will discuss the full range of paramagnetic nanostructures up to 25 x 25 sizes over the thermal energy range from 0.01 to 0.1. To estimate the spatial impact range of the nanostructures, we also investigated the spatial correlation factor for each case. In addition, we also compute the spatial magnetic susceptibility and heat capacity of the device. References: 1. Tyagi, P.; Riso, C.; Friebe, E., Magnetic Tunnel Junction Based Molecular Spintronics Devices Exhibiting Current Suppression At Room Temperature. Organic Electronics 2019, 64, 188-194. 2. Savadkoohi, M.; Dahal, B. R.; Grizzle, A.; D'Angelo, C.; Tyagi, P., Interaction between magnetic molecules and two ferromagnetic electrodes of a magnetic tunnel junction (MTJ). Journal of Magnetism and Magnetic Materials 2021, 529, 167902.

A Monte Carlo Study of Paramagnetic Nanostructure Coupled with Two Ferromagnetic Electrodes of a Cross-Junction Shaped Spintronics Device at Different Thermal Energies

When paramagnetic molecules covalently bond to a ferromagnet (FM), they undergo extensive hybridization with the surface and result in a spin-polarized molecule-ferromagnet interface. The resulting ferromagnet-molecule hybridization leads to a wide range of active functionalities, such as energy-level control and spin filtering capabilities . Magnetic tunnel junction-based molecular spintronics devices (MTJMSDs) are fabricated by bridging monolayers of molecules across the MTU's tunnel barrier, where they chemically bond with the FM electrodes. Thus, MTJMSDs become a highly promising testbed for controlled spintronics at room temperature MTJMSD testbed also allows the molecule-ferromagnet interface to become a significant spin pathway enabling new equilibrium density of states over long range’ ”’ Understanding the role of spin fluctuations in MTJMSD with various types of metallic electrodes is exceptionally challenging. We conducted theoretical studies to understand the free electrons spin effect on MTJMSD magnetization using 3D Heisenberg-based Monte Carlo simulations. For this study, we varied the electron spin in 1) ferromagnetferromagnet, 2) ferromagnet-paramagnet, and 3) ferromagnet-antiferromagnet electrode pairs. In general, we found that as the magnitude of free electrons spin in the electrodes and molecules increased, the device magnetization increased when the free electron had parallel coupling with its host atom. Conversely, the total device magnetization decreased for antiparallel electron-atom coupling. Interestingly, long-range ordering in antiferromagnetic electrodes diminished with antiparallel electron-atom coupling and was enhanced with parallel coupling for a free-electron spin of equal magnitude at room temperature. In this study, we also recorded the correlated distribution of the devices’ magnetic moment to elucidate the spatial impact range of molecules as a function of free electron spin. We also explored the electron spin effect on magnetic susceptibility and heat capacity. This research may inform the designing of novel molecular spintronics devices by providing a knowledge base about the impact of free electron spin for varying electrode materials. This research is supported by National Science Foundation-CREST Award (Contract # HRD- 1914751), Department of Energy/ National Nuclear Security Agency (DE-FOA-0003945). 1. A. Cornia and P. Seneor, Nature Materials 16 (5), 505-506 (2017). 2. P. Tyagi, C. Riso, U. Amir, C. Rojas-Dotti and J. Martinez-Lillo, RSC Advances 10 (22), 13006-13015 (2020). 3. P. Tyagi, C. Riso and E. Friebe, Organic Electronics 64, 188-194 (2019).

Spin Fluctuation Effect on Magnetic Tunnel Junction-Based Molecular Spintronics Devices (MTJMSD)

High-performance thermoelectric materials are currently being sought after to recycle waste heat. Copper chalcogenides in general are materials of great interest because of their naturally low thermal conductivity and readily modifiable electronic properties. The compounds Cu5Sn2Q7 were previously reported to have metal-like properties, which is not a desirable characteristic for thermoelectric materials. The aim of this study was to reduce the carrier concentration of these materials by Zn-doping, and then investigate the electronic and thermoelectric properties of the doped materials in comparison to the undoped ones. The compounds were synthesized using both the traditional solid-state tube method and ball-milling. The crystal structures were characterized using powder X-ray diffraction, which confirmed that all materials crystallize in the monoclinic system with the space group C2. With the partial substitution of zinc for copper atoms, the compounds exhibited an overall improvement in their thermoelectric properties. Figure of merit values were determined to be 0.20 for Cu4ZnSn2Se7 at 615 K and 0.05 for Cu4ZnSn2Te7 at 575 K

Zinc Multi-Pnictogens Semiconductors—Cu Doping and Thermoelectric Characteristics

Boron nitride (BN) nanotube is an anisotropic nanomaterial that possess unique intrinsic properties like high thermal conductivity, electrically insulating, high oxidation resistance, superior mechanical strength, and piezoelectric property. The incorporation of the BN nanotubes in polymer has created opportunities to produce composites with a wide range of possible applications like aerospace applications, thermal interface material. However, the improved properties of these composite like thermal transport ability are still far from expected and theoretical stipulations due to the random orientation of these nanotubes with excellent in-plane properties and poor out-of-plane properties. Therefore, controlling the orientation of the nanotubes in the composite is important for optimizing its performance. This paper focused on the magnetic modification of boron nitride nanotubes for their alignment in polymer composite. The magnetic modification of the BN nanotube is carried out by functionalizing nanotubes with iron oxide nanoparticles (magnetite) which produces paramagnetic BN nanotubes. These functionalized BN nanotubes exhibit magnetic responses that can enable control over their orientation and position under low external magnetic fields in low viscous fluids. The BN nanotubes are modified through electrostatic interaction with the iron oxide nanoparticles, therefore, preserving their intrinsic properties and structure. The paramagnetic nanotubes are to be dispersed in polymer fluid, controlled with magnets, and cured to maintain nanotubes' position and alignment. The magnetic functionalization of BN nanotubes can provide the ability to spatially manipulate these nanotubes into more complex networks crucial for applications in nanoelectronics, sensors, spintronics, and thermoelectric devices. It can also enable the fabrication of anisotropic composite materials with improved directional property and high thermal transport ability.

Magnetic Modification of Boron Nitride Nanotubes for Alignment in Thermal Interface Composite

As the complexity of flexible electronic devices such as displays and sensors has increased, new plastic-compatible manufacturing methods are becoming necessary to produce high-yield, low-defect flexible circuits. While solution-processed methods such as printing can be used to fabricate circuits on low-temperature substrates, printing is not always a feasible option to realize complex, high-density circuits with small devices. In particular, highresolution display applications typically require single-micron feature sizes and excellent uniformity over large-area substrates. For these applications, more precise fabrication techniques such as photolithography are required. However, due to the poor dimensional stability of polymers, even low-temperature processes such as soft bakes during lithography can alter the substrate dimensions. The problem of dimensional stability can be overcome by attaching the polymer film to a rigid carrier during device fabrication, then releasing the polymer substrate with the fully fabricated device layer on top. For this reason, the separation of polymer films from rigid carriers remains a crucial step in creating next-generation flexible electronics. In this talk, we will discuss a large-area, high-throughput photonic lift-off (PLO) process to rapidly separate polymer films from rigid carriers. PLO uses broadband light (200 nm — 1100 nm) from a flashlamp to lift off a polymer film from a rigid carrier coated with a light-absorbing layer (LAL), where the polymer film may contain functional devices [1]. Compared to a raster process such as excimer laser lift-off, the PLO process is advantageous as it can enable large area lift-off (150 mm x 75 mm) in one flash of light lasting between 100- 200 us, thus enabling higher throughput. Furthermore, the LAL prevents direct illumination of the polymer substrate during lift-off and facilitates cleaner lift-off without polymer ashing. The LAL also makes PLO a polymer-agnostic process, enabling lift-off of a wide range of polymers. We will discuss our recent work fabricating flexible thin-film transistors (TFTs) using PLO [2]. Polyimide with a low coefficient of thermal expansion (CTE) was used to minimize residual film stress. Indium zinc oxide (IZO) TFTs were fabricated on the polyimide films and subsequently released from the carrier using PLO. The released devices demonstrated no significant changes after the PLO process, yielding a mobility of ~3 cm“V_s__ before and after liftoff. The flexible TFTs were robust to bending stress, showing no notable decrease in mobility while bent with a 10 mm radius of curvature. When combined with the ability to successfully separate the PI from the carrier, the low-CTE PI creates a robust fabrication platform for flexible electronics that allows conventional patterning and deposition techniques to be used on a plastic substrate while maintaining dimensional stability with processing temperatures up to 380 °C. A 3D finite element model indicates that the polymer/LAL interface reaches above 800 °C during PLO, but the top surface of the PI remains below 120 °C. The model shows that the maximum temperature at the device layer during PLO is strongly impacted by the thickness and material properties of the polymer film, highlighting the value of the model to guide PLO device design. This work demonstrates the feasibility of PLO to successfully release polyimide substrates containing flexible electronic devices from glass carriers after withstanding conventional lithographic processing methods. [1] R. Hendriks and K. A. Schroder, “Method for performing delamination of a polymer film. U.S. Patent 10,011,104.,” U.S. Patent 10,011,104, Jul. 03, 2018 [2] A. M. Weidling, V. S. Turkani, V. Akhavan, K. A. Schroder, and S. L. Swisher, “Large-Area Photonic Lift-off Process for Flexible Thin-Film Transistors,” in press.

Large-Area Photonic Lift-off Process for Flexible Thin-Film Transistors

In recent years, oxide electronics has emerged as one of the most promising new technologies for a variety of electrical and optoelectronic applications, including next-generation displays, solar cells, batteries, and photodetectors. Oxide electronics have a lot of potential because of their high carrier mobilities and ability to be manufactured at low temperatures. However, the preponderance of oxide semiconductors is n-type oxides, limiting present applications to unipolar devices and stifling the development of oxide-based bipolar devices like p-n diodes and complementary metal-oxide—semiconductors. We have contributed to oxide electronics, particularly on transition metal oxide semiconductors of which the cations include In, Zn, Sn and Ga. We have integrated these oxide semiconductors into thin film transistors (TFTs) as active channel layer in light of the unique combination of electronic and optical properties such as high carrier mobility (5-10 cm“/Vs), optical transparency in the visible regime (>~90%) and mild thermal budget processing (200-400°C). In this study, we achieved four different results. The first result is that unlike several previous reports on oxide p-n junctions fabricated exploiting a thin film epitaxial growth technique (known as molecular beam epitaxy, MBE) or a high-powered laser beam process (known as pulsed laser deposition, PLD) that requires ultra-high vacuum conditions, a large amount of power, and is limited for large-area processing, we demonstrate oxide-based heterojunction p-n diodes that consist of sputter-synthesized p-SnOx and n-IGZO of which the manufacturing routes are in-line with current manufacturing requirements. The second result is that the synthesized p-SnOx films are devoid of metallic Sn phases (i.e., sn? state) with carrier density tuneability and high carrier mobility (> 2 cm2/Vs). The third result is that the charge blocking performance of the metallurgical junction is significantly enhanced by the engineering of trap/defect density of n-IGZO, which is identified using photoelectron microscopy and valence band measurements. The last result is that the resulting oxide-based p-n heterojunction exhibits a high rectification ratio greater than 10° at +3 V (highest among the sputter-processed oxide junctions), a low saturation current of ~2x10 © A, and a small turnon voltage of ~0.5 V. The outcomes of the current study are expected to contribute to the development of p-type oxides and their industrial device applications such as p-n diodes of which the manufacturing routes are in-line with the current processing requirements. Reference: 1. Lee, S.; Paine, D. C., Metallization selection and the performance of amorphous In-Zn-O thin film transistors. Applied Physics Letters 2014, 104 (25), 252103. 2. Liu, M.; Kim, H.; Wang, X.; Song, H. W.; No, K.; Lee, S., Carrier Density-Tunable Work Function Buffer at the Channel/Metallization Interface for Amorphous Oxide Thin-Film Transistors. ACS Applied Electronic Materials 2021, 3 (6), 2703-2711. 3. Chu, X., Zhuang, S., Chi, C., Xu, H., Du, G., Dong, X., & Yin, J. (2017). Study on the electroluminescence properties of the P-nimgo:Li/mgo/n-zno nanowires/ito heterojunction. Journal of Luminescence, 187, 486-491. 4. Kawazoe, H.; Yanagi, H.; Ueda, K.; Hosono, H., Transparent p-Type Conducting Oxides: Design and Fabrication of p-n Heterojunctions. MRS Bull. 2000, 25 (08), 28-36. 5. Mo, X., Fang, G., Long, H., Li, S., Wang, H., Chen, Z., Huang, H., Zeng, W., Zhang, Y., & Pan, C. (2014). Unusual electroluminescence from n-ZnO@i-MgO core-shell nanowire color-tunable light-emitting diode at reverse bias. Phys. Chem. Chem. Phys., 16(20), 9302-9308. 6. Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H., Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. Nature 2004, 432 (7016), 488-492.

Facile Processing and Properties of P-Type SnOx and Oxide-Based p-n Heterojunction Application with n-InGaZnO

The role of band-tail states (BTS) on the operation of |GZO TFTs is well established, however there is wide variation in the interpretation of the interaction and/or independence of channel mobility and charge trapping. In many reports the influence of BTS on the level of free charge is accounted for by an effective mobility which is dependent on the applied gate bias. While this may accurately match current-voltage characteristics, this treatment is lumping together the effects of charge trapping and carrier scattering which should remain distinct. When these effects are combined, a model which can accurately represent device behavior over a wide temperature range is not possible due to fundamental differences in temperature dependence. Bottom-gate TFTs were fabricated with a 50 nm IGZO film sandwiched between a 50 nm gate oxide and a 50 nm passivation oxide layer. The working metal was molybdenum for the gate electrode and source/drain contacts. A passivation anneal was done and a capping layer was added to promote electrical stability; full process details are provided in a previous report. Devices were tested using a Lakeshore cryogenic probe station, with transfer characteristic measurements taken from room temperature to below 100 K. Electrical measurements made on long-channel devices (L = 12 um) has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. An |GZO TFT device model has been recently developed using Silvaco Atlas, which accounts for the role of donor-like oxygen vacancy defects, acceptor-like BTS, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. The temperature-dependent mobility follows a power-law relationship, resembling behavior consistent with ionized defect scattering. The mobility model is independent of carrier concentration, without dependence on the applied gate bias. Details of the material and device model, and associated defect distribution parameters will be presented.

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