United States

Electronic devices that can simulate the dynamics of neurotransmission in the human body are of great interest for the development of artificial intelligence in modern information technology. In this paper, an artificial nociceptor realized by a single metal-oxide nanobelt device with a unique capacitive-coupled threshold switching behavior is demonstrated. Via thermal admittance spectroscopy and temperature dependent sweeping study, the properties of the nanobelt devices are determined by Schottky emission at low bias and by defect assisted quantum tunneling at high bias subject to a threshold voltage. The low activation energy associated with dynamic electron trapping gives rise to a voltage-dependent volatile threshold switching behavior. This threshold switching behavior allows the emulation of several characteristic features of a nociceptor, a critical type of sensory neuron in the human body, including “threshold”, “relaxation”, “no adaptation”, “allodynia” and “hyperalgesia” behaviors, essential for the realization of electronic sensory receptors that detect noxious stimuli and signal rapid warning to the central nervous system. One-dimensional metal oxide nanobelt devices of this type yield multifunctional nociceptor performance that is fundamental for applications in artificial intelligence systems, representing a key step in the realization of neural integrated devices via a bottom-up approach.

Materials Challenges for Memory

Threshold Switching in Single Metal‐Oxide Nanobelt Devices Emulating an Artificial Nociceptor

single nanobelt device

charge trapping/detrapping

threshold switching

nociceptor

artificial synapse


![](https://assets.underline.io/uploads/markdown_image/1/image/2e10c515564e9ec3287ee4c664011c20.png)

The energy cost of storing and moving data is enormous, and is growing at such a rapid pace that within a few years the power demand may overwhelm some developed nations. Non-volatile memory (NVM) and neuromorphic computing are enabling critical advances in this area, but there are many scientific and technological challenges. This conference will cover the materials challenges of different memory technologies, from the fundamental processes and mechanisms, to industry perspectives on materials specifications and manufacturing.

poster

One of the most desirable attributes of non-volatile memories and memristors is a fast and non-destructive readout of their resistive state. Prototypical ferroelectric memories use the bulk photovoltaic response associated to the polarization of ferroelectric films to address this requirement by optically sensing binary memory cells. A more advanced type of non-volatile memories are ferroelectric tunnel junctions. They feature resistive state ratios RHigh/RLow of 10^6, with an accessible continuum of resistive states, making them promising candidates for neuromorphic computing applications. However, tunnel junctions have ultrathin ferroelectric barriers in the range 3-6 nm that prevented a measurable photovoltaic response originated in the bulk of the barrier. We present the optical sensing of the resistive state of a ferroelectric tunnel junction using the Schottky barrier formed in the bottom interface to dramatically enhance its optical response. Our FTJ based on the La0.7Sr0.3MnO3/BaTiO3 (LSMO/BTO) interface, one of the best performing and studied material combinations, builds up an optically active Schottky barrier whose properties can be tuned by performing a resistive switch. By integrating a transparent conducting top electrode of ITO, we make the junctions optically accessible to light. UV illumination with 3.3 eV energy, exceeding the BTO bandgap, generates a solid photovoltaic response in the high resistance state originated in the Schottky barrier, with an open circuit voltage Voc of 0.4 V at 20 K. The photovoltaic effect is absent using lower energy red light (1.9 eV). In the RLow state, the Schottky barrier is removed and the photo response disappears, enabling the optical sensing of the resistive state.


Optically Active Schottky Barrier in La0.7Sr0.3MnO3/BaTiO3/ITO Ferroelectric Tunnel Junction Memories

Development of complementary metal–oxide–semiconductor (CMOS) logic is expected to approach its fundamental limit as the scaling down of the CMOS technology is reaching an end. As a route to extend the technology roadmap beyond traditional CMOS logic, novel spin-based logic architectures are being developed to provide nonvolatile data retention, near-zero leakage, and scalability. In particular, architectures based on magnetic domain walls (DWs) take the advantage of the fast motion, high density, non-volatility and flexible design of DWs to process and store information. Such schemes have so far relied on DW manipulation and clocking using an external magnetic field, which hinders their implementation in dense, large-scale chips. Here we demonstrate a method for performing all-electric logic operations and cascading using DW racetracks. Our concept for the magnetic DW logic is based on efficient DW motion induced by spin-orbit torques (SOTs) and recently developed chiral coupling between adjacent magnets where the magnetic anisotropy competes with the interfacial Dzyaloshinskii–Moriya interaction (DMI). Our work provides a viable platform for scalable all-electric magnetic logic, paving the way for memory-in-logic applications.

Current-driven magnetic domain-wall logic

Non-volatile memories include magnetic random access memories (MRAM), reverse transfer magnetoresistive random access memory (STT-MRAM), phase change random access memory (PCRAM), and resistive random access memory (RRAM), the latter being non- volatiles emerging. The RRAMs memories are characterized for having a metal/insulator/metal architecture; however, we proposed an alternative configuration based on metal/oxide-diluted magnetic semiconductors (O-DMS)/metal due to the promising magnetic control performance of resistive switching. This work presents a study of the structural, morphological, magnetic, and electric properties of Cobalt doped ZnO and TiO2 thin films fabricated via DC magnetron sputtering. HR-SEM and AFM micrographs evidencing the formation of small grains in the surface associated with the growth mechanism for the thin films. Electrical and magnetic characterization shows a contribution of lattice-free electrons, produced for oxygen vacancies, and Co ions randomly located into oxide semiconductor matrix, in the SET and RESET states. Comparative study of ZnO and TiO2 semiconductor matrices suggestion the low energy consumption in the process and the expansion of storage capacity, due to both high and low resistive states modified for the magnetic field applied.

Cobalt doping effect on ZnO and TiO2 Based on Resistive Switching Memory Device

In this work, we present structural, morphological, magnetic, and electrical properties of GaSb/Mn multilayer deposited via DC magnetron sputtering at room temperature and 423 K. Through Raman measurements, it was possible to determine the formation of p-type GaSb layers. HR-SEM shows the multilayer architecture with columnar microstructure in the formation of layers with grain nucleation in the surface. The effect of the substrate temperature contributed to the stress effects on the layers. Formation of the interlayers between GaSb and Mn layer was determined via Rutherford Back-Scattering spectra. These interlayers were associated with diffusion process during deposition and contributed to the magnetic behavior of multilayers. A ferromagnetic-like behavior was observed in the multilayers associated to the domains formation due to the interlayers presence. I-V curves show a RESET-SET states of multilayer system with bipolar behavior, which can be modified from external magnetic fields.


GaSb/Mn Multilayers Via DC Magnetron Sputtering: A Study of Interface Structure for Non-Volatile Memories Applications

Resistive switching memories are a serious contender for high density computing memory in the future. The operation of valence change memories specifically relies on a migration of defects within the oxide layer. This is assumed to be the case in our silicon dioxide devices[1]. It is therefore crucial we understand the properties of the migrating defects, such as their mobilities, so that we can simulate devices more effectively and with better precision. We are investigating a phenomenon observed within oxide capacitors known as the current transient[2] as one potential mechanism to probe defect mobilities and their effect on interface barriers. 
The current transient phenomenon arises when a constant voltage is applied to a leaky oxide capacitor causing a distinctive transient to be observed. The device current initially increases rapidly up to a maximum, then levels out, and finally decays slowley. This results in a characteristic peak observed in the current-time plot. Although we have previously used it to carry out computations[3], it has also been suggested that oxygen vacancy mobilities can be obtained from such transients[4] by analysing the dynamics using a space charge limited current (SCLC) model[2,5]. However, our investigations into this effect suggest that the SCLC theory may not be an accurate representation of the changes occurring within our own devices. 
To investigate the validity of the SCLC model we have developed techniques to repeatably induce current transients within devices as well as novel analytical techniques that reveal more information on the dynamics of the transient. In doing so, we have been able to develop an alternative model that may help explain the current transient as a two-part process which is the result of charge injection and a field drive migration of defects occurring in parallel.
While this model differs to the SCLC theory, it still predicts defect mobility to be a measurable observable and may provide a more accurate representation of this quantity. Additionally, it may allow us to determine interface barrier heights at the source of electron injection - something which cannot be determined from the SCLC analysis. 
Our new approach to analysing current transients may prove to be an important probe into the dynamics of defects within resistive switching memories.

1 A. Mehonic, M.S. Munde, W.H. Ng, M. Buckwell, L. Montesi, M. Bosman, A.L. Shluger, and A.J. Kenyon, Microelectronic Engineering 178, 98 (2017).
2 A. Many and G. Rakavy, Physical Review 126, 1980 (1962).
3 D.J. Mannion, A. Mehonic, W.H. Ng, and A.J. Kenyon, Frontiers in Neuroscience 13, 1386 (2020).
4 S. Zafar, R.E. Jones, B. Jiang, B. White, P. Chu, D. Taylor, and S. Gillespie, Applied Physics Letters 73, 175 (1998).
5 M.A. Lampert and P. Mark, (1970).




Improving the accuracy of defect mobilities and observing interface effects of resistive switching memories using the current transient phenomenon

Vanadium dioxide (VO2) has been widely studied for its prominent insulator-metal transition (IMT) near room temperature and potential applications in novel memory devices and brain-inspired neuromorphic computing. We report on the fabrication of in-plane VO2 metal-insulator-metal (MIM) structures and reproducible switching measurements in these two-terminal devices. The VO2 film grown on TiO2 (001) substrate by pulsed laser deposition (PLD) was etched into bridge structures with different sizes. Resistive switching can be achieved by applying current/voltage bias, which creates Joule heating in the device and triggers the IMT. We observe repeatable volatile switching and a clear correlation between the switching power and device size. Here, we also report that our memory element is capable of multi-level storage in a single cell. By adjusting the compliance and voltage bias, we are able to freely and reliably move between these intermediate levels. This approach provides a gateway to mimic neurons and synapses with hardware components, allowing for much denser and complex neural networks.

Multi-level operation in VO2 resistive switching devices

Magnetoelectric materials have very broad prospects in sensors, next-generation memory devices, etc. However, the practical application of magnetoelectric exchange films is still challenged by many factors, such as the substrate clamping effect, the leakage problem, and the large bias field. In response to the above challenges, we have taken the following three measures. First, we adopted a vertically aligned nanocomposite (VAN) structure instead of the traditional multilayer structure to overcome the substrate clamping effect and achieve an efficient strain coupling. Secondly, we chose the less leaky Na0.5Bi0.5TiO3 instead of BiFeO3 as the ferroelectric matrix. A p-n junction formed at the film-substrate interface, which further suppressed the vertical leakage current in the nanocomposite film. The low leakage enables the in-situ electric field control of magnetic properties in the ultra-thin multiferroic composite film in a large scale. In the Na0.5Bi0.5TiO3 -CoFe2O4 VAN, the obtained magnetoelectric coefficient is as high as 1.32x10-9 s m-1. Finally, we introduced the antiferromagnetic phase, i.e. NiO, into the traditional ferrimagnetic-ferroelectric two-phase multiferroic composite film to form a three-phase Na0.5Bi0.5TiO3-NiO-NiFe2O4 VAN film, where a self-biased magnetoelectric effect was achieved via the antiferromagnetic-ferromagnetic exchange coupling. These studies have paved the way to the practical application of composite multiferroic thin films in electronic devices, such as magnetoelectric random memory (MeRAM).

Approach to the practical magnetoelectrics with the vertically aligned nanocomposites

In this work we investigate the effect of annealing in different atmospheres (inert: Ar; and reducing: H₂/N₂) towards optimising the electrical operation of Pt/TiOx/Pt devices. Overall, annealed devices exhibit lower operating voltages and more prominent hysteretic behaviour. Additionally we are exploring the effect of the process in both the crystalline structure of said devices as well as on the top Pt/TiOx interface. By carefully tuning the annealing temperature and conditions we can transition from an amorphous film to a microcrystalline and subsequently to a fully crystalline one with pronounced characteristic anatase peaks.


Interface effects of annealing processes on TiO2-based memristive devices

A metal barrier layer (BL) is usually inserted between the top electrode and oxide layers to enhance the cycle-to-cycle uniformity in electrochemical metallization cell (ECM) devices.[1–3] Nevertheless, the oxidation of the metal layer at the BL/oxide interface cannot be avoided.[4] This newly formed oxide interfacial layer influences the switching characteristics of the devices, and, thus, the thickness of the BL should be optimized to achieve the desired uniformity.[5] However, these studies[1–5] do not conduct a comparative observation employing various metal layers that could elucidate the origin of such switching modification. In this work, we explore various metals as a barrier layer in the Ag/ZnO/Pt stack ECM cells. We found that the improvement of cycle-to-cycle uniformity found in the devices made with BL is always accompanied by the increase of set voltage variability and the decrease of the memory window. Materials analysis is conducted, and switching mechanisms are proposed to explain this trade-off phenomenon.

Reference
1 D. Panda, F.M. Simanjuntak, S. Chandrasekaran, B. Pattanayak, P. Singh, and T.-Y. Tseng, IEEE Trans. Nanotechnol. 19, 764 (2020).
2 S. Lim, S. Lee, J. Woo, D. Lee, A. Prakash, and H. Hwang, ECS Solid State Lett. 4, Q25 (2015).
3 C.-A. Lin, C.-J. Huang, and T.-Y. Tseng, Appl. Phys. Lett. 114, 093105 (2019).
4 S. Chandrasekaran, F.M. Simanjuntak, T.-L. Tsai, C.-A. Lin, and T.-Y. Tseng, Appl. Phys. Lett. 111, 113108 (2017).
5 S. Chandrasekaran, F.M. Simanjuntak, R. Aluguri, and T. Tseng, Thin Solid Films 660, 777 (2018).

Role of the metal barrier layer in switching characteristics of digitally switched ZnO-based electrochemical metallization cells

ULTRARAM™ is an emerging charge-based memory that is non-volatile whilst also having ultra-low-energy logic-state switching.1,2 These seemingly contradictory properties are achieved by a triple-barrier resonant tunnelling (TBRT) structure, which utilises the extremely large InAs/AlSb conduction band offset (2.1 eV). Much like flash memory, ULTRARAM™ uses a floating gate to store charge, with non-destructive read of the logic state by a proximate channel. However, due to the TBRT structure only 2.5 V is required to program/erase, which is an order of magnitude lower than flash. Switching times and endurance are predicted to be similar to DRAM. ULTRARAM™ has many potential applications including conventional computing (large-scale and personal), artificial intelligence and the internet-of-things. However, for these to be realised, low-cost mass production must be achieved, necessitating growth on 300-mm Si substrates. Growth of III-V’s on Si presents challenges related to differences in lattice constant, thermal expansion coefficients and the polar/non-polar interface. These degrade epilayer quality due to the formation of threading defects and anti-phase domains.3

Here we report on recent progress on the growth of the III-V ULTRARAM™ on Si substrates by molecular beam epitaxy (MBE). A high-quality GaSb surface is required prior to deposition of the In(Ga)As and AlSb memory epilayers. Several growth techniques, including migration-enhanced epitaxy, interface-misfit epitaxy and two-step temperature growth were used to form two different buffer structures on 4˚ offcut substrates: (A) GaSb/GaAs/Ge/Si, where the Ge layer was deposited by chemical vapour deposition, and (B) GaSb/AlSb/Si, where all layers were grown by MBE. A comparison of these buffer layers, as well as a GaSb/GaAs control sample, is shown in the table below. The GaSb/AlSb/Si buffer was found to have the highest quality surface, exceeding that of the control sample grown on GaAs, and was used for growth of the full memory structure (TEM images below). This material has been processed into the first ULTRARAM™ memories on Si, with testing currently underway.

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