United States

Using a W-line with Cu injectors, we analyzed the impact of thermal gradients on Cu interconnects lifetime. Self-heating was experimentally assessed, and Cu temperature was estimated through an electro-thermal model. Experimentally, we find a low EM-EA~0.8eV, suggesting other failure mechanisms. Our 1D physics-based model predicts 3x faster void nucleation for EM+TM and a corrected EA~0.89eV, closer to the measured EM-EA. This finding allows a more reliable lifetime estimation under operating conditions with high thermal gradients.

IRPS 2024 Main Conference

De-coupling Thermo-migration from Electromigration using a dedicated test structure

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

poster

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Impacts of BEOL queue time (Q-Time) from post-Cu CMP (Chemical Mechanical Polish) to SiCN capping layer on reliability were investigated. Degradation in electromigration (EM) was observed in both Cu/Low-k (LK) and Cu/Ultra-low-k (ULK) interconnects due to Cu surface oxidation. However, there is no reliability impact in LK dielectric, while significant degradation in ULK dielectric. EM degradation in long CMP Q-Time could be recovered by CMP Buff process.

Impacts of Post-Cu CMP Queue Time on Reliability

In this work, we explored the self-heating effect (SHE) and performance analysis of Backside Power Delivery Network (BSPDN) technology for routing logical signals from underlying devices to SRAM macros and 3nm technology nodes. A comprehensive evaluation was conducted on the impact of using BSPDN on the thermal effects and performance of circuits in terms of Power, Performance, Area, and Thermal (PPAT) from devices to circuits.

Self-Heating Effect of Device-Circuit with Back-side Power Delivery Network beyond 3nm Node

In this work, the impact of read scheme together with polarization state of the ferroelectric (FE) domains on the interface trap behavior of FeFETs for NOR array applications were investigated. Hf0.5Zr0.5O2 (HZO)-based FeFET with different interfacial layer (IL) treatments were used for the analysis. It is found that the trap energy will move closer to the Fermi energy as VG increases and higher VD can help to suppress the read operation induced IL degradation.

Investigation of Read Disturb for Hf0.5Zr0.5O2 Ferroelectric Field-Effect Transistors Based Neuromorphic Applications

For memory and in-memory computing applications, the multi-level cell (MLC) is one of the most favorable characteristics of RRAM. However, achieving stable MLCs demands time-consuming programming strategy. This paper presents a novel programming algorithm, Adaptive Step Adjustment Programming (ASAP), implemented on 1Mb RRAM chips fabricated using 40nm CMOS technology. Our experimental results showcase remarkable improvement in 16-level MLC programming efficiency. The MLC retention characteristics exhibit good stability after 104 s thermal stress at 150 ℃.

ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell

This paper addresses the correct analysis of thick-oxide devices that mimic HV periphery devices of 3DNAND. Thick oxides grown close to the STI are found to be thinner at the edges. We introduce a model that divides the oxide into three different regions with different EOTs. This explains the conflicting electrical data and highlights the role of corners on leakage and breakdown. Applying the model to different oxide-growth processes provides guidelines to limit thickness variations.

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics

DRAM reliability issues, including static data retention and tRDL, have proven challenging as interface trap density increases through scaling. Some ionic charges, such as chlorine and hydrogen, are inevitably in-flowed in DRAM cells during Trench Sidewall Silicon Oxide (Trench-Ox) process. These ionic charges not only serve as traps but also have negative impact on DRAM structure. In this paper, we propose a novel interface engineering of Trench-Ox that improves reliability and wiggled patterns of DRAM.

Interface Engineering of Trench-Ox for Modern DRAM Devices

Temperature affects performance, power and energy efficiency of system-on-chips (SOC). In this work, Monte Carlo (MC) calibrated device transport models are used to study thermal effects on block level PPA using imec's A14 technology. Self-heating raises the SOC operational temperature (T) as function of the power (P). At the same time, that power itself varies with temperature. An electrothermal model is used to account for this P-T interdependency and to obtain a final self-consistent solution.

Thermal Performance Evaluation of Multi-core SOCs Using Power-Thermal (P-T) Co-simulation

High-energy X-rays are used in PCB inspection systems to ensure electrical connectivity between components. The X-rays used in these systems often have energy ranging from a few keV to 150 keV. Exposure to these X-rays can cause a shift in individual transistor parameters due to total-ionizing dose (TID) effects. This damage is characterized for commercial PCB inspection systems along with mitigation techniques.

Total-Ionizing Dose Damage from X-Ray PCB Inspection Systems

We propose a radiation-hardened FF combined with a transient-fault tolerant (TFT) structure and fabricated test chips in a 65 nm FD-SOI technology. Experimental results show that the soft error rate of the proposed TFT FF is three orders of magnitude lower than that of a standard FF. The TFT FF has 35% area, 15% delay and 9% power overhead, and its energy-delay product is half as large as a conventional stacked FF.

A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead

Single event cross section trends are investigated at near-threshold-voltage (NTV) supply voltages for different VT options and RHBD flip flop designs at the 5-nm bulk FinFET node. Results show very different responses for each design yielding a wide range of choices for meeting design specifications.

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Impacts of Post-Cu CMP Queue Time on Reliability

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