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The use of hardware caches became essential in modern embedded systems to address the speed gap between processor and memory. In such systems, cache-related preemption delay (CRPD) may represent a significant proportion of task execution time. Addressing this delay in scheduling simulation of these systems stays an open and under-examined problem. Assumptions are often made to simplify the computation model used in simulation and capture the worst-case effect. Nevertheless, they can introduce situations in which scheduling simulation is considered not only pessimistic but also non-sustainable. In this article, we discuss the problem and propose a less pessimistic CRPD computation model that allows sustainable scheduling simulation regarding the capacity parameter. With the proposed model, a system that is schedulable with simulated worst-case execution times remains so when these parameters are reduced. These results improve the applicability of scheduling simulation in the early verification stage for systems with caches. Experiments conducted with our CRPD computation model show a 5% to 12% improvement of schedulability task set coverage and a 30% to 50% reduction of preemption cost with regard to existing CRPD computation models. An integration in a scheduling simulator and a performance evaluation are also realized for the proposed model.

AEiC 2021 - 25th Ada-Europe International Conference on Reliable Software Technologies

Feasibility interval and sustainable scheduling simulation with CRPD on uniprocessor platform

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### Welcome Message from our Co-Chairs

Through this message, we want to give you our warmest welcome to the 25th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2021). The special circumstances we all go through have made the conference a virtual event. Nonetheless, this will allow us to take advantage of the benefits of this format by using the Underline.io platform that allows remote participation of speakers and attendees and a virtual exhibition.
The platform will also provide a virtual space through Gather.Town to facilitate social interaction among participants, which, in addition to presenting state of the art research results, is one of the most important goals of a conference. This platform will hold various social events together with breaks and a poster session. 

The conference schedule includes a four-day program and exhibition from Monday to Thursday, with parallel tutorials on Monday, and keynotes, technical sessions and a Work-in-Progress session on the remaining three days. The technical sessions include the presentations of 13 journal-track papers, 5 industrial presentations and 6 invited talks on leading topics on reliable software technologies. The program will be completed with three outstanding keynotes that will delight the participants.

The main conference activities will be from 13:00 to 18:00 Central European Summer Time (CEST) to allow participants from America to Central Asia to attend to the conference sessions. Virtual social events are scheduled at the beginning and the end of each day. We encourage you to participate in these activities as well as visiting the exhibition. We look forward to meeting you virtually in June 2021!

**J. Javier Gutiérrez and Mario Aldea Rivas**
 // AEiC 2021 Program Co-Chairs

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technical paper

This paper presents the implementation of Queuing
Ports, a blocking communication protocol developed
for many-core architectures that perform a synchronized communication between cores without the need
of polling. This implementation has been performed on
M2OS-mc, a Real-Time Operating System (RTOS) that
has already been tested in the Epiphany processor. The
extension presented is based on the ARINC-653’s Queuing Port communication primitive and gives an alternative to the implementation based in the ARINC-653’s
Sampling Port communication primitive previously developed.1
Keywords: many-core, queuing-port, epiphany, task
synchronization, M2OS

Queuing ports for mesh based many-core processors

This paper describes the Ember library for highintegrity embedded robotics and GNC applications developed in SPARK 2014 with formal verification. The
library is based on generic packages and includes functionality as linear algebra, complex numbers, quaternions, and kinematics. Preliminary test results for linear
algebra performance are very promising.
Keywords: Numerics, robotics, embedded, SPARK

Ember: An embedded robotics library in SPARK

Global static scheduling (one scheduling table generated off-line per processor) for Mixed Criticality (MC) systems demonstrate excellent results in terms of acceptance ratio and number of preemptions. But, no practical implementation and empirical evaluation have been presented yet for multi-processors systems. In this paper, we present two contributions on the implementation of global static schedulers for MC systems to enforce low latency mode changes. This work interest is illustrated scheduling scheduling tables produced by GMH_MC_DAG, a meta-heuristic to compute schdeduling tables for multi-periodic Directed Acyclic Graphs of Mixed Criticality tasks with multiple criticality level.

Contributions to the implementation of global schedulers for mixed-criticality systems

The Robot Operating System (ROS/ROS2) is a de facto standard in many fields of robotics research, with increasing 
presence in the industry. RCLAda is a binding to the ROS2 framework that enables programming for ROS2 in pure 
Ada with seamless integration into the ROS2 workflow. 
During this tutorial, participants will learn how to install ROS2 and RCLAda, the necessary basic information about 
the ROS2 build system and RCLAda integration, and will program basic examples and simulated mobile robots of the 
kind used in the DARPA Subterranean Challenge

Programming mobile robots with ROS2 and the RCLAda Ada Client Library

This tutorial presents the fundamental notions that make the development of safety‐critical software different from 
the development of more casual software. It presents the context, the applicable standards, and the techniques used 
for achieving high reliability. It explains why Ada and Spark are especially suited for writing safety‐critical software. 
Although required for demanding applications, the general principles that are detailed can be applied to, and help 
improve, all kinds of software development.

Introduction to the development of safety‐critical software

OpenMP is one of the most widely used frameworks for the development of parallel programs. OpenMP provides a set 
of annotations which allows for a compiler (or pre‐processing tool) to generate parallel code from sequential code (C, 
C++ or Fortran), as well as a runtime that manages the concurrency and parallel execution (usually on top of a 
multithreaded OS). 
The forthcoming revision of Ada specifies a lightweight parallel model, through a set of constructs that provide a guide 
to the compiler, to generate the required code for the parallel execution. This lightweight model maps well to one of 
the OpenMP approaches, which allows parallel Ada programs to execute on top of OpenMP runtimes, as well as roll‐ 
your‐own light‐weight thread schedulers. 
This tutorial will show how to develop Ada parallel programs, using both OpenMP as well as a light‐weight thread 
scheduler.

Parallel programming with Ada and OpenMP

The objective of this tutorial is to explain how to apply timing verification from design models at an early stage to 
verify their timing requirements, avoiding the late discovery of costly timing errors. The tutorial will introduce the 
tools and techniques used to produce design models that, though being useful for code generation, shall be also able to 
be trustily subject to a suitable form of timing verification. Depending on the severity of the need for verification the 
design models will be restricted and furtherly transformed so as to serve as input to either (hard) schedulability 
analysis, or (soft) simulation techniques. The seminar will address first a panoramic view of the field, then it will 
describe the concepts, languages, tools, and techniques involved, mainly related to the UML and MARTE standards, 
and finally show their application by means of a well‐known industrial case study from the avionics domain. In 
addition, pedagogical exercises will be proposed to the attendees to fix concepts and train the usage of the tools.

Timing verification from UML & MARTE design models: techniques & tools

Many multicore processors are capable to speedup computations with a significant magnitude, reducing for example 
to one hour some computation that would otherwise take an entire day to complete. The Ada programming language 
provides a high level and effective tool to speedup computations on multicore processors. The design of parallel 
programs starts with the granularity level of the parallelism with careful attention to memory management. We 
decide on the size of each job, check the mapping of jobs to threads, and on the location of the input and output data 
for each job. In the evaluation of parallel programs we tune the work load to reach the desired level of efficiency and 
throughput

Programming shared memory computers

The increasing computational capacity of cyber‐physical systems (CPS) due to more powerful processors and, 
especially, multi‐core systems has caused their implementation in control systems to have a greater impact than 
initially expected. One of the consequences is the inclusion of a large number of CPS in the development of cars, 
airplanes, trains, etc. The need to reduce consumption, weight, wiring, etc., in these systems has led to the integration 
of the multiple functions performed in a system in a few computing platforms. In this line of development, 
hypervisors play a relevant role in the design, development and certification of the system. Hypervisors allow to 
integrate in the same computing platform the different functionalities that are performed in dedicated CPS. The aim of 
this presentation is to show that the use of hypervisors for CPS development presents fundamental advantages in the 
design, development and certification with respect to more traditional CPS systems.

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Queuing ports for mesh based many-core processors

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Feasibility interval and sustainable scheduling simulation with CRPD on uniprocessor platform